深入分析单片机复位问题

背景

实际项目应用过程中，碰到单片机异常复位的问题，一般log数据也没法存储下来，问题比较难分析。实际项目中遇到的是英飞凌CY 芯片发生复位，查实际问题ECU也有RES_CAUSE 复位原因记录。

芯片RES_CAUSE

数据手册中Reset 可能原因的记录

CYT4BF can be reset from a variety of sources, including software. Most reset events are asynchronous and guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT, software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and allows software to determine the cause of the reset. An XRES_L pin is available for external reset.

CYT4BF重启原因很多，包括软件。大多数重置事件都是异步的，并保证恢复到已知状态。复位原因：

POR:(Power On Reset) 上电复位 上电复位的基本原理是通过特定的电路配置，在电源电压上升并稳定之前，利用电容和电阻的特性，使单片机的复位引脚经历从高电平到低电平的变化，从而实现微控制器的复位操作，确保其能够正确启动并运行程序。

BOD： Brown-Out Detection 欠压监测复位

OVD: Overvoltage detection 过压复位

过流: 过流引起复位

XRES_L：芯片RESet引脚，Active LOW external reset input

WDT: 看门狗定时器复位

MCWDT：多计数器看门狗定时器复位；WDT和MCWDT的主要区别在于实现方式和计数器数量。WDT使用单一计数器来监控系统运行，而MCWDT则通过多个计数器提供更灵活和精确的系统监控能力。

软件复位：即通过将Cortex™-M3中断应用和复位控制寄存器中的SYSRESETREQ位置’1’，实现软件复位。STM32官方已经将软件复位过程给封装好了，即 NVIC_SystemReset() 函数，NVIC_SystemReset()函数的内容如下

干货：手把手指导单片机复位原因分析_rcc_flag_pinrst-CSDN博客

如上文章是以STM32 为例，官方都有封装好的软件复位函数进行调用就行，完成软件复位。

故障：相关物理故障导致复位发生。

CSV： Clock Supervisor ，时钟监测复位

Hibernate唤醒：休眠唤醒复位

调试：调试复位

记录在寄存器中，通过复位可以保持，并允许软件确定复位原因。XRES_L引脚可用于外部复位。

不同bit 位的原因记录如下：

Description: Reset Cause Observation Register
Address: 0x40261800
Offset: 0x1800
Retention: Retained
IsDeepSleep: Yes
Comment: Indicates the cause for reset(s) that occurred in the system. All bits in this register assert when the corresponding reset cause occurs and must be cleared by firmware. Low-voltage cause bits are reset whenever the low-voltage supply is initialized, including XRES, POR, brown-out, and during Hibernate wakeup. HT products also clear low-voltage cause bits for over-voltage,over-current, and WDT resets. Refer to the reset source documentation to understand what reset source behavior for different configuration or modes.
Default: 0x40000000

显示系统发生复位的原因。当相应的复位原因发生时，该寄存器中的所有位都断言，并且必须由固件清除。当低压电源初始化时(包括 XRES、POR、browout和Hibernate唤醒期间)，低压原因位被重置。HT产品还可以清除过压、过流和WDT复位的低压触发位。请参考重置源文档，了解不同配置或模式下的重置源行为。

Bits	Name	SW	HW	Default or Enum	Description
0	RESET_WDT	RW1C	A	0	A basic WatchDog Timer (WDT) reset has occurred since last power cycle. ULP products: This is a low- voltage cause bit that hardware clears when the low- voltage supply is initialized (see comments above). For products that support high-voltage cause detection, this bit blocks recording of other high- voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits.
1	RESET_ACT_FAULT	RW1C	A	0	Fault logging system requested a reset from its Active logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above). 故障记录系统要求从其活动状态重新设置逻辑。这是一个低电压导致位的硬件低压电源初始化后清除
2	RESET_DPSLP_FAULT	RW1C	A	0	Fault logging system requested a reset from its DeepSleep logic. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).
3	RESET_TC_DBGRESET	RW1C	A	0	Test controller or debugger asserted reset. Only resets debug domain. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).
4	RESET_SOFT				A CPU requested a system reset through it's SYSRESETREQ. This can be done via a debugger probe or in firmware. This is a low-voltage cause bit that hardware clears when the low-voltage supply is initialized (see comments above).软复位，SYSRESETREQ置1
5-8	RESET_MCWDT0 -T3				Multi-Counter Watchdog timer reset
16	RESET_XRES	RW1C	A	0	External XRES pin was asserted. This is a high- voltage cause bit that blocks recording of other high- voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. This bit is not blocked by other HV cause bits. 外部引脚拉低复位。
17	RESET_BODVDDD	RW1C	A	0	External VDDD supply crossed brown-out limit. Note that this cause will only be observable as long as the VDDD supply does not go below the POR (power on reset) detection limit. Below this limit it is not possible to reliably retain information in the device. This is a high-voltage cause bit that blocks recording of other high-voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. 欠压复位
18	RESET_BODVDDA				External VDDA supply crossed the brown-out limit.
19	RESET_BODVCCD				内部VCCD核心电源超过了断电限制。
20	RESET_OVDVDDD				过压监测
21	RESET_OVDVDDA				VDDA过压监测
22	RESET_OVDVCCD				VCCD过压监测
23	RESET_OCD_ACT _LINREG				过流监测
24	RESET_OCD_DPSLP _LINREG				过流监测
25	RESET_OCD_REGHC				过流监测
26	RESET_PMIC	RW1C	A	0	PMIC status triggered a reset. If PMIC control is not present, hardware will never set this bit. This is a high- voltage cause bit that blocks recording of other high- voltage cause bits, except RESET_PORVDDD. Hardware clears this bit during POR. PMIC 复位
28	RESET_PXRES				PXRES triggered 复位
29	RESET_STRUCT_XRES				Structural reset was asserted.
30	RESET_PORVDDD				Indicator that a POR occurred. This is a high-voltage cause bit, and hardware clears the other bits when this one is set. It does not block further recording of other high-voltage causes. 上电复位发生